Class Information

Calendar

Projects

Additional Reading

Other Resources

Acknowledgments

Class Information

Instructor: Arjan Durresi (durresi@csc.lsu.edu). TA This graduate course focuses on the techniques of quantitative analysis and evaluation of modern computing systems, such as the selection of appropriate benchmarks to reveal and compare the performance of alternative design choices in system design. The emphasis is on the major component subsystems of high performance computers: pipelining, instruction level parallelism, memory hierarchies, input/output, and network-oriented interconnections. In addition to the textbook, this course includes a number of readings from research papers. The course will involve a semester-long project. Homework Reading will be assigned for each lecture. Before lecture, every student must submit a one page report of the assigned papers (report should contain a one paragraph summary of the paper, description of three strong points of the paper and three weak points of the paper). The reports are due one hour before the class starts (DUE TIME: 12:30 PM), by email, include 7080 and the homework number in the subject. Homework can be submitted by email to me at durresi@csc.lsu.edu, include 7080 - HW# in the subject. IMPORTANT: Submit your homework in PDF format or txt and include in the file's title: 7080, HW#, Your name. Efficient Reading of Papers in Science and Technology Project Every student must complete a project on one of the topics discussed in the class. Students are required to work in teams of two on the project. In addition to the presentation given in the class every team will meet with me to discuss the accomplished results and asses the contribution of each team member. Every project must have a practical component that will require you to do an implementation and demonstration. Textbook John L. Hennessy, David A. Patterson "Computer Architecture: A Quantitative Approach" Third Edition, Morgan Kaufmann, 2002, ISBN: 1558605967 Class Schedule and Office Hours TTh 1:40-03:00pm 220 TUREAUD HALL, Arjan Durresi: Tu 3-4 and Th 3-4 Coates Hall 291 Class Roster

Calendar

Week Tuesday Thursday January 16-20 Course overview and topics 2 slides per page 6 slides per page Introduction to Computer Architecture 2 slides per page 6 slides per page January 23-27 Introduction to Computer Architecture 2 slides per page 6 slides per page Introduction to Computer Architecture: Instructions 2 slides per page 6 slides per page January 31 - February 1 Performance of Computer Systems 2 slides per page 6 slides per page The Case for te Reduced Instruction Set Computer David A. Patterson, David R. Ditzel Comments on "The Case for te Reduced Instruction Set Computer," By Patterson adn Ditzel Douglas W. Clark, William D. Strecker Performance of Computer Systems 2 slides per page 6 slides per page David Patterson and Carlo Sequin, RISC I: A Reduced Instruction Set VLSI Computer in Proceedings of the International Symposium on Computer Architecture (ISCA) 1981, James Smith and Andrew Pleszkun, Implementation of Precise Interrupts in Pipelined Processors in Proceedings of the International Symposium on Computer Architecture (ISCA) 1985 Gurindar Sohi and Sriram Vajapeyam, Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors in Proceedings of the International Symposium on Computer Architecture (ISCA) 1987 February 6-10 Performance of Computer Systems 2 slides per page 6 slides per page Instruction Sets & Pipelines 2 slides per page 6 slides per page Readings due February 9, 2006: R. Tomasulo, An Efficient Algorithm for Exploiting Multiple Arithmetic units IBM Journal, January 1967 Jack Dennis and David Misunas, A Preliminary Architecture for a Basic Data-Flow Processor Proceedings of the International Symposium on Computer Architecture (ISCA) 1975 Gregory papadopoulos and David Culler, Monsoon: an Explicit Token-Store Architecture Proceedings of the International Symposium on Computer Architecture (ISCA) 1990 February 13-17 Instruction Sets & Pipelines 2 slides per page 6 slides per page Instruction Sets & Pipelines 2 slides per page 6 slides per page February 20-24 Memory & Caches 2 slides per page 6 slides per page Reading due February 21: Brian Fields, Shai Rubin, Rastislav Bodik, Focusing Processor Policies via Critical-Path Prediction in Proceedings of the 28th International Symposium on Computer Architecture (ISCA 2001) , James Smith, Decoupled Access/Execute Computer Architectures in Proceedings of the International Symposium on Computer Architectures (ISCA), 1982 Richard Russel, The CRAY-1 Computer System Communications of the ACM, 21(1) 63-72, January 1978 Memory & Caches 2 slides per page 6 slides per page Reading due February 23: Subbarao Palacharla, Norman P. Jouppi and J. E. Smith,, Complexity-effective superscalar processors in Proceedings of the 24th International Symposium on Computer Architecture (ISCA). Denver, 1997 , Joseph Fisher, Very Long Instruction Word Architectures and the ELI-512 in Proceedings of the International Symposium on Computer Architecture (ISCA), 1983 Tse-Yu Yeh and Yale Patt, Alternative Implementations of Two-level Adaptive Branch Prediction Proceedings of the International Symposium on Computer Architecture (ISCA), 1992 March 6-10 Memory & Caches 2 slides per page 6 slides per page Writing a Research Paper 2 slides per page 6 slides per page March 13-17 Memory & Caches 2 slides per page 6 slides per page Embedded Architectures 2 slides per page 6 slides per page March 20-24 Embedded Architectures 2 slides per page 6 slides per page Reading due March 21: Jason Hill, Robert Szewczyk, Alec Woo, Seth Hollar, David Culler, Kristofer Pister, System Architecture Directions for Networked Sensors Jason Hill and David Culler, A wireless embedded sensor architecture for system-level optimization Embedded Architectures 2 slides per page 6 slides per page March 27-31 Issues in Basic Pipelines (stalls, exceptions, branch prediction) 2 slides per page 6 slides per page Modern Supercomputing Reading due March 30: 1) Aad J. van der Steen, Jack J. Dongarra, Overview of Recent Supercomputers 2) KEITH D. UNDERWOOD, WALTER B. LIGON III and RON R. SASS, An Analysis of the Cost Effectiveness of an Adaptable Computing Cluster Additional and Optional Material: Jack J. Dongarra, Present and Future Present and Future: Supercomputer Architectures and their Interconnects Cray Links to Supercomputer Architectures Information High Performance Computing: A Short Tour through Supercomputers, Clusters, and Grid Computing April 3-7 2 slides per page 6 slides per page Reading due April 4: (1) Dean Tullsen, Susan Eggers, and Henry Levy, Simultaneous Multithreading: Maximizing On-Chip Parallelism, Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995 (2) Steve Swanson, Luke McDowell, Michael Swift, Susan Eggers, Henry Levy, An Evaluation of Speculative Instruction Execution on Simultaneous Multithreaded Processors, ACM Transactions on Computer Systems, Vol. 21, No. 3, August 2003, Pages 314-340. 2 slides per page 6 slides per page Readings due April 6, 2006: Armando Fox and David Patterson, Self-Repairing Computers, Appears in Scientific American, June 2003 (1) David Patterson, Aaron Brown, et. all, Recovery Oriented Computing (ROC): Motivation, Definition, Techniques, and Case Studies, UC Berkeley Computer Science Technical Report UCB//CSD-02-1175, March 15, 2002. (2) Oppenheimer, D., A. Brown, et. all, ROC-1: Hardware Support for Recovery-Oriented Computing, IEEE Transactions on Computers, vol. 51, no. 2, February 2002. April 10-14 No Class. Sprint break. No Class. Sprint break. April 17-21 Reading due April 18: (1) Todd Mowry, Monica Lam, and Anoop Gupta, Design and Evaluation of a Compiler Algorithm for Prefetching, Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 1992 (2) Subbarao Palacharla and R.E. Kessler, Evaluating Stream Buffers as a Secondary Cache Replacement, , Proceedings of the International Symposium on Computer Architecture (ISCA-21), 1994. Readings due April 20, 2006: (3) M. Blaum, J. Brady, J. Bruck and J. Menon, EVENODD: an optimal scheme for tolerating double disk failures in RAID architectures Proceedings of the 21st International Symposium on Computer Architecture (ISCA), 1994 (4) David patterson, Garth Gibson, and Randy Katz, A Case for Redundant Arrays of Inexpensive Disks (RAID), ACM SIGMOD conference, 1988 April 24-28 2 slides per page 6 slides per page Reading due April 27 (No summary due): (1) Ajit Narayanan, Quantum computing for beginners Proceedings of the Congress on Evolutionary Computation, 1999. (2) Dean Copsey, Mark Oskin, Francois Impens, Tzvetan Metodiev, Andrew Cross, Frederic T. Chong, Isaac L. Chuang, and John Kubiatowicz, Toward a Scalable, Silicon-Based Quantum Computing Architecture, Appears in Journal of Selected Topics in Quantum Electronics, Vol 9, No. 6, pp 1552-1569. November/December 2003 (3) Leonard Adleman, Molecular Computation of Solutions to Combinatorial Problems, Science Magazine, Vol 266, November 11, 1994. May 1-5 Reading due May 2 (No summary due): (4) Mark Oskin, Frederic T. Chong, Isaac L. Chuang, and John Kubiatowicz. Building Quantum Wires: The Long and the Short of it, Appears in Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003). (5) Daniel Lenoski, James Laudon, Truman Joe, David Nakahira, Luis Stevens, Anoop Gupta, and John Hennessy, The DASH Prototype: Implementation and Performance, Proceedings of the International symposium on Computer Architecture, 1992. (6) Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David Kranz, John Kubiatowicz, Beng-Hong Lim, Kenneth Mackenzie, and Donald yeung, The MIT Alewife Machine: Architecture and Performance, Proceedings of the International symposium on Computer Architecture, 1995

Class Projects

Additional Resourses

Set of Problems 1 60th anniversary of the unveiling of ENIAC WWW Computer Architecture Home Page Online version of classic architecture book  Computer structures: readings and examples [Compiled by] C. Gordon. The SimpleScalar simulator is a very flexible simulation package that comes with a working version of GCC and precompiled  versions of the SPEC 95 benchmark suite.  SimpleScalar comes with several different simulators, each of which supports a different level of simulation: everything from timing-free but fast simulation (for debugging), to a full out-of-order simulator.  The simulated processor is a variant of the MIPS architecture.

Other Resources

Kevin G. Hayes Effective Research Presentations Mark D. Hill Oral Presentation Advice

Acknowledgments

The lecture notes have incorporated course materials developed by:

Louisiana State University Department of Computer Sciences